Fast-sensing amplifier for flash memory

ABSTRACT

A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.

RELATED APPLICATIONS

[0001] This application is a Divisional of U.S. patent application Ser.No. 09/642,953, filed Aug. 21, 2000, which is a Divisional of U.S.patent application Ser. No. 09/136,909, filed Aug. 20, 1998, now issuedas U.S. Pat. No. 6,108,237, which is a Continuation of U.S. patentapplication Ser. No. 08/895,618, filed Jul. 17, 1997, now issued as U.S.Pat. No. 5,835,411, which is a Continuation of U.S. patent applicationSer. No. 08/804,951, filed Feb. 24, 1997, now issued as U.S. Pat. No.5,862,077. All of these applications are incorporated herein byreference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to the field ofelectrically programmable and electrically erasable read-only memories,and more particularly, to a fast-sensing amplifier for a flash memorydevice.

BACKGROUND OF THE INVENTION

[0003] In recent years, the use of personal computers has growntremendously in nearly all aspects of society. Personal computerstypically comprise a microprocessor chip, random access memory, andnon-volatile memory. Non-volatile memory is memory that retains itsstored information even when power is no longer supplied to the chip.One type of non-volatile memory is flash memory, which can be botherased and programmed electrically.

[0004] In non-volatile complementary metal-oxide semiconductor (CMOS)read-only flash memories employing floating-gate memory devices, amemory array consisting of a number of these devices is customarilycoupled to a common sensing circuit through a column line connecting thedrains of the individual memory devices and a word line connecting thegates of the devices in the array, to comprise a memory circuit.Typically a charged column line remains charged if the memory devicecoupled to it is nonconductive. If coupled to a conductive memorydevice, the line discharges. The sensing circuit, or amplifier,determines the binary state (conductive or nonconductive) of the memorydevice based on whether the line is charged or not.

[0005] A floating-gate memory device typically requires limiting themaximum potential at the column line to a potential significantly lessthan the voltage applied to the word line during read, or sense,operations. This minimizes disturbing the data stored on the floatinggate of a device during read operations. Usually within a non-volatileflash memory device, the voltage swing on the column line between a highbinary state and a low binary state is quite small. This reduction involtage swing on the capacitive load on the column line of the memoryarray decreases the access time needed to determine the binary state ofa device, but brings about the need for an amplifier circuit to furtherseparate the swing between a low binary state and a high binary state.The amplifier circuit also limits the maximum voltage at the column lineduring read operations. Although using an amplifier circuit itself addsan amplifying step that increases access time, the net effect stillserves to decrease access time as compared to a memory circuit with noamplifier but having a large voltage swing on the large capacitance ofthe memory column lines. This is because minimizing the voltage swingbetween a high and low binary state typically reduces read-access timemore than the inclusion of an amplifying step increases access time.

[0006]FIG. 1A is a system-level depiction of one prior art approach toCMOS high-speed sensing. The sensing circuit, or amplifier, consists oftwo read-biasing and amplifying circuits coupled to a differentialamplifier. Generally, after the column line of a desired memory devicewithin the memory array is selected, the differential amplifier comparesthe charge, or voltage, of the selected device to a sensing-referencecharge, or voltage. The differential amplifier amplifies the differencebetween the voltage at the selected memory device and thesensing-reference voltage. This difference corresponds to the binarystate of the device.

[0007] In a typical read, or sensing, operation, the column line of thememory array often discharges substantially when coupled to a conductivememory device. Before another read cycle can occur, the line must berecharged. The recharging period retards access time in these memorycircuits because of the considerable parasitic capacitance generallyassociated with the lines. The greater capacitance of longer linesexacerbates this problem in larger memory circuits. A drawback of theprior art is that the capacitance of the reference column effectivelydoubles the capacitance that needs to be recharged. In some instances,this delays access time over the time needed just to recharge the columnline of the selected memory device.

[0008]FIG. 1B depicts in further detail one prior art approach toimplementing the read-biasing and amplifying circuit in FIG. 1A.Transistors P1, P2, P3, N1, N2, and N3 make up a typical amplifier withfeedback biasing, to maintain the selected column line at a stablevoltage during sensing. Prior to a read operation, CP, a clock pulsedhigh, discharges the selected column line to ground. During this time,transistor N12 isolates the column line of the selected memory devicefrom the biasing circuit. Upon CP going low, the memory devicereconnects to the biasing circuit, and transistor N2 quickly charges thecolumn line to near the sensing-reference level. The feedback path thenturns N2 off and current-loading transistor P3 supplies the finalcharging current.

[0009] Another drawback to the prior art is the complexity of thisread-biasing and amplifying circuit. The large number of transistors inthe amplifying circuit, consisting of transistors N1, N2, N3, P1, P2,and P3, lengthens memory read-access time due to the parasiticcapacitances of the transistors themselves and the delays they cause.Still another drawback is that isolating the memory array from thebiasing circuit before a read operation via transistor N12 furtherdelays read-access time. Moreover, N12 loads the circuit with additionalcapacitance, which also increases access time.

SUMMARY OF THE INVENTION

[0010] The present invention provides for a fast and efficient MOSsensing amplifier for sensing the binary state of floating-gate memorydevices within a floating gate memory array having a column lineselectively coupled to the devices. Prior to sensing, the column linedischarges quickly to ground. During a sense operation, a read-biasingand amplifying circuit quickly pulls up the column line to the sensepotential at the selected memory device. A differential amplifiercompares this sensed potential to a sense-reference potential, providingas output the binary state of the selected memory device.

[0011] The above summary of the present invention is not intended topresent each embodiment or every aspect of the present invention. Thisis the purpose of the figures and the associated description thatfollow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other aspects and advantages of the present invention will becomeapparent upon reading the following detailed description and uponreference to the drawings described below.

[0013]FIG. 1A is an electrical schematic showing on a system level aprior art sensing means for flash memory.

[0014]FIG. 1B is an electrical schematic showing in more detail theprior art sensing means of FIG. 1A.

[0015]FIG. 2 is an electrical schematic showing a differential amplifiercircuit compatible with the present invention.

[0016]FIG. 3 is an electrical schematic showing a read-biasing andamplifying circuit compatible with the present invention.

[0017]FIG. 4 is an electrical schematic showing a high-speed sensingcircuit compatible with the present invention.

[0018]FIG. 5 is an electrical schematic showing an alternativeembodiment read-biasing and amplifying circuit using a p-channelquick-charging transistor compatible with the present invention.

[0019]FIG. 6 is a waveform diagram showing the operation of thehigh-speed sensing circuit shown in FIGS. 3 and 4.

[0020]FIG. 7 is an electrical schematic showing an alternativeembodiment read-biasing and amplifying circuit using an n-channelquick-charging transistor compatible with the present invention.

[0021]FIG. 8 is a block diagram of a typical computer that mayincorporate the present invention.

[0022] While the invention is susceptive to various modifications andalternate forms, specifics thereof have been shown by way of example inthe drawings and will be described in detail. It should be understood,however, that the intention is not to limit the invention to theparticular embodiment described. On the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificembodiments in which the invention may be practiced. It is to beunderstood that other embodiments may be utilized and structural changesmay be made without departing from the scope of the present invention.For instance, the present invention has application in connection withnon-volatile read-only memory erasable by ultraviolet light andelectrically programmable (EPROM) and also electrically erasable andprogrammable read-only memory (EEPROM) chips. In addition, thedifference amplifier circuits for sensing the difference between thetarget memory cell and the reference memory cell may be implementedusing various forms of active or passive circuits, and the respectivecircuits providing the input and output signals may be implemented in anumber of modified forms. The preferred circuits depicted in FIG. 4 showan exemplary arrangement and use a high-speed sensing means inaccordance with the present invention, but it should be recognized thatother circuits may be implemented within the scope of the presentinvention without loss of generality.

[0024]FIG. 2 depicts a typical differential amplifier circuit that maybe used with the present invention. The difference amplifier has a firstinput line, a second input line, and an output line. A sensing referencesignal from a reference memory cell is compared to a source signal fromone of the memory array column lines, and the binary state of the sourcememory cell is the output of the amplifier. The source and n-well ofp-channel metal-oxide semiconductor field-effect transistors (MOSFETs)P21 and P22 are coupled to a predetermined voltage Vcc, with the gatesof P21 and P22 coupled to the drain of P22 and the drain of n-channelMOSFET N22 and the gate of n-channel MOSFET N24. The drain of P21couples to the drain of n-channel MOSFET N21 and the gate of n-channelMOSFET N25. The first input line is coupled to the gate of N21, and thesecond input line is coupled to the gate of N22. The sources of N21 andN22 are connected to the drain of n-channel MOSFET N23, which has itssource coupled to predetermined voltage Vss and its gate coupled topredetermined voltage Vbias and the gate of n-channel MOSFET N26. N26has its source coupled to Vss, with its drain coupled to the sources ofN24 and N25. The source and n-well of p-channel MOSFETs P23 and P24 arecoupled to a predetermined voltage Vcc, with the gates of P23 and P24coupled to the drain of P23 and the drain of N24. The drain of P24 iscoupled to the drain of N25 and the output line.

[0025] The difference amplifier separates further the relatively lowvoltage swing between a binary high state and a binary low state thatmay be stored in a memory device. The reference memory device willsupply at the negative (−) input of the differential amplifier apredetermined sensing-reference voltage upon Vbias going high. Theselected memory device within the memory array will supply at thepositive input a voltage either slightly lower or slightly higher thanthe reference voltage, depending on whether the device represents abinary low or binary high state, respectively.

[0026] If the memory device represents a binary low state, the voltageit supplies to the positive input of the differential amplifier will beslightly less than the voltage supplied by the reference device to thenegative input. The difference between the voltage supplied by thedevice and the voltage supplied by reference device will be slightlyless than zero. The output of the differential amplifier will thereforebe low, because the voltage across the positive and negative terminalsis not a positive voltage.

[0027] If the memory device represents a binary high state, the voltageit supplies to the positive input of the differential amplifier will beslightly greater than the voltage supplied by the reference device tothe negative input. The difference between the voltage supplied by thedevice and the voltage supplied by the reference device will be slightlyhigher than zero. The output of the differential amplifier willtherefore be high, because the voltage across the positive and negativeterminals is positive.

[0028]FIG. 3 illustrates a new and novel read-biasing and amplifyingcircuit compatible with the present invention. The read-biasing andamplifying circuit has an input line Din and an output line Dout.P-channel MOSFETs P31, P32, and P33 each have their source and n-wellcoupled to the predetermined voltage Vcc. The gates of P31 and P32couple to each other and the predetermined voltage Vss, and the drainsof P32 and P33 couple to each other and the gate of P33 and Dout. Thesource of n-channel MOSFET N31 couples to the predetermined voltage Vss,and the drain of N31 couples to the gate of n-channel MOSFET N32 and thedrain of P31. The gate of the N31 couples to Din and the source of N32.The drain of the N32 couples to the drains of P32 and P33 and the gateof P33 and Dout.

[0029] The read-biasing and amplifying circuit used is a new and novelapproach. The quick-charging transistor for biasing the bit line forsensing is the p-channel transistor, P33. This device operates in thesaturated region of operation for quick charging of the bit line and is“off” during sensing. During sensing, transistor P32, which is in thelinear region of operation, provides current and acts as the load forthe memory cell being sensed. Transistors N3 1, N32 and P31 form afeedback biasing circuit which limits the bit line voltage duringsensing. Limiting the bit line voltage during read operations isrequired by the floating-gate memory cells to prevent read disturbs.This circuit is an improvement over prior art because the feedbackbiasing circuit consists of only three transistors, rather than five ormore as in prior art, and therefore is faster. Having a fast feedbackpath is also important in preventing overshoot of the bit line duringcharging because overshoot can cause additional delays during sensing.Furthermore, the quick-charging device not only charges the bit linenode but also provides quick charging of the read-biasing and amplifyingcircuit's output node, Dout. This again results in a speed improvementover the prior art. Also, with the sensing load operating in the linear,or resistive, region of operation rather than in saturation mode, thevoltage differential to the differential amplifier is more linear withmemory cell currents. This results in a more equal voltage differencefor the same amount of current difference between the reference currentand the memory cell stored “one” and “zero” states.

[0030] Within the preferred embodiment of the invention, the new andnovel biasing circuit acts to quickly pull up the input line to the biaspotential needed during the sensing of the data stored on a selectedmemory device, and to prevent overshoot on this line that wouldotherwise result from such a fast pull up. The input line Din initiallydischarges to ground. Afterwards, with transistor P32 serving as a loadto the memory device coupled to the input line, transistor P33 acts as aquick-charging device to quickly pull the input line up to the read-biaspotential used in reading the selected memory device. The feedbackcircuit comprised of transistors N31, P31, and N32 prevent the inputline from overshooting the read-bias potential on the memory devicecoupled to the line.

[0031] For example, if the selected memory device coupled to the lineinput Din has no charge on its gate (corresponding to a logic zero), thedevice will conduct. Transistor P33 will quickly raise the potential atthe line until transistor N31 turns on, which in conjunction withtransistors P31 and N32 will ensure that the potential at the input linedoes not rise above Vss plus the threshold voltage of transistor N3 1.By preventing the input line from rising above this potential, thefeedback circuit limits the maximum voltage in the bit lines at thememory cells. Dout will stabilize at a predetermined voltage less thanthe reference voltage, and will output to the differential amplifier apotential representing binary low.

[0032] If on the other hand the selected memory device coupled to theline input Din has a negative charge on its gate (corresponding to alogic one), the device will either be off or will only slightly conduct,at a lesser current level than the reference device. Transistor P33 willquickly pull up the potential at the line until transistor N31 turns on,which in conjunction with transistors P31 and N32 will ensure that thepotential at the input line does not rise above Vss plus the thresholdvoltage of transistor N31. Again, by preventing the input line fromrising above this potential, the feedback circuit limits the maximumvoltage on the bit lines of the memory cells. Dout will stabilize at apredetermine voltage greater than the reference voltage, and will outputto the differential amplifier a potential representing binary high.

[0033]FIG. 5 shows an alternative embodiment with an enable control,{overscore (E)}. This sensing circuit operates similar to the preferredembodiment, except that the gate of P31 couples to an enable line,{overscore (E)}, and an additional n-channel MOSFET transistor N33 hasits drain coupled to the gate of N32, its source coupled to Vss, and itsgate also coupled to the enable line. Upon {overscore (E)} going low,transistor P31 turns on and N33 turns off, which enables the feedbackcircuit to turn on when Din is coupled to a selected memory device. When{overscore (E)} goes high, a sensing operation cannot occur. TransistorN33 turns on and P31 turns off, which in turn prevents transistor N32from turning on. Since transistor N32 connects the quick-chargingtransistor P33 to the input line Din, if N32 does not turn on, then Doutwill not reflect the potential at Din. Therefore, essential to thecorrect operation of the alternative embodiment is for {overscore (E)}to go low when a sensing operation is to occur.

[0034]FIG. 7 shows yet another alternative embodiment with an enablecontrol, {overscore (E)}. This alternative embodiment is identical tothat depicted in FIG. 5, except that an n-channel MOSFET N50 supplantsthe p-channel transistor P33 in FIG. 5 as the quick-charging device. Thedrain and gate of transistor N50 couple to the predetermined voltageVcc, while transistor N50's source couples to output line Dout. Otherthan this modification, the alternative embodiment of FIG. 7 operatesidentically to the embodiment portrayed in FIG. 5. Because n-channeltransistors have a higher transconductance than p-channel transistors,employing an n-channel transistor as the quick-charging device resultsin less capacitive loading on the device itself (viz., lessself-loading) than if using a p-channel transistor. The ensuingadvantage is that the read-biasing and amplifying circuit operates morequickly than if the quick-charging device were a p-channel transistor.

[0035] In addition to the read-biasing and amplifying circuit, theinvention consists of the sensing arrangement described in FIG. 4. Asensing reference is provided by a p-channel MOSFET P41 with the sourceand n-well coupled to the predetermined voltage Vcc, and the gate anddrain coupled to the second input line of the difference amplifier. Afirst read-biasing and amplifying circuit has its output line coupled tothe gate and drain of the P41 and the second input line of thedifference amplifier and a sense reference. N-channel MOSFETs N50 andN51 are coupled in series connection, with the gates of N50 and N51being connected to the predetermined voltage Vcc, the drain of the N51coupled to the source of the N50, and the drain of the N50 coupled tothe input line of the first read-biasing circuit. A referencefloating-gate memory device has the source coupled to a predeterminedreference source, the gate coupled to a reference bias voltage Vrefbiasand the drain coupled to the source of transistor N51.

[0036] The sensing reference is not a reference column in the array, butrather is a single cell. It is biased with a voltage, Vrefbias, whichcontrols the reference current to which the memory cells are compared. Asingle reference can be used by one or by multiple differential senseamps. In a typical implementation, a plurality of sense amplifiers canshare a single reference. Since this results in more loading on thesense reference line, an additional quick-charging transistor, P41, maybe added to the sense reference signal.

[0037] In this sensing circuit, PCL, a clock pulsed high, pulls the bitlines low prior to sensing, as shown in FIG. 6. For improvedperformance, the bit lines are not disconnected from the read-biasingand amplifying circuit. This improves performance because the bit linesdo not have any additional delay or loading from an isolation devicegated by PCL. This does have the disadvantage of drawing current throughthe read-biasing and amplifying circuit during the time of pulling thebit lines low. However, this current can be controlled by proper sizingof the quick-charging devices. This arrangement has an additional speedadvantage resulting from not using the memory cells to discharge the bitlines from the programmed cell read-bias level to the erased cellread-bias level. The additional speed advantage is achieved by bringingthe addressed word line high while PCL is discharging the bit lines.Once PCL has gone low, the read-biasing and amplifying circuit willquickly pull the selected bit lines to the read-bias levels. If thememory cell being read is an erased cell, then it will be conductingcurrent and the bit line will not be pulled as high as if the cell isprogrammed. A programmed cell is either conducting no current orsignificantly less current than the erased cell. The high-speed sensingcomes from the combination of the bit lines being pre-charged low, whilethe word line being accessed, and the strong pull up and biasing speedof the read-biasing and amplifying circuit.

[0038] In other words, the new and novel approach of the invention liesin quickly discharging the bit line to a potential close to ground, andthen quickly charging the line back up to the read-bias levels withoutdischarging the line with the selected memory devices. In the preferredembodiment, the bit line Din discharges to ground upon the clock pulsePCL going high. After the bit line goes low, and upon the clock pulsePCL going low, the sensing amplifier quickly pulls the potential of theline to the read-bias potential of the selected memory device. Thefeedback circuit of the sensing amplifier limits overshoot considerably.If the selected memory device carries no charge on its floating gate(viz., it is an “erased” cell), overshoot never exceeds thepredetermined reference voltage. Furthermore, if the selected memorydevices carries a negative charge on its floating gate (viz., a“programmed” cell), overshoot is essentially negligible. FIG. 6 alsoshows how Dout and Din indicate either a low or high binary statevis-a-vis the sense-reference potential. Din and Dout are relativelylower than their respective reference potentials when indicating abinary low stored on a memory device, and are relatively higher whenindicating a binary high.

[0039]FIG. 8 is a block diagram of an exemplary computer 45 that mayincorporate the present invention. The computer 45 includes amicroprocessor 46 and corresponding clock 48. The microprocessor 46contains the central processing unit (CPU) and associated controlcircuitry. The microprocessor 46 is connected to a motherboard 49. AnI/O interface module 47 is connected to the motherboard 49 andinterfaces the microprocessor 46 with peripheral devices such as amonitor and printer. The motherboard 49 also contains a plurality ofmemory modules for storing data, such as single in-line memory modules(SIMMs) 50A-50N. The motherboard 49 is typically implement with aprinted circuit board, and the SIMMs 50A-50N are typically implementedwith integrated circuit chips which “plug into” the motherboard 49. Anonvolatile memory is usually used on the motherboard 49, SIMMs 50A-50N,or through the I/O interface module 47.

[0040] The foregoing description, which has been disclosed by way of theabove examples and discussion, addresses preferred embodiments of thepresent invention encompassing the principles of the present invention.The embodiments may be changed, modified, or implemented using variouscircuit types and arrangements. For example, the difference amplifiercircuit for sensing the difference between the target memory cell andthe reference memory cell may be implemented using various forms ofactive or passive circuits, and the respective circuits providing theinput and output signals may be implemented in a number of modifiedforms. Those skilled in the art will readily recognize that these andvarious other modifications and changes may be made to the presentinvention without strictly following the exemplary embodiments andapplications illustrated and described herein, without departing fromthe true spirit and scope of the present invention which is set forth inthe following claims.

What is claimed is:
 1. A read-biasing circuit for sensing the binarystate of a floating-gate memory device and having an input line and anoutput line, comprising: a quick-charging circuit operatively coupled tothe input line and the output line which quickly raises the potential ofthe input line to a predetermined first voltage if the device is in onebinary state and to a predetermined second voltage if the device is inits other binary state and the potential of the output line to apredetermined third voltage if the device is in one binary state and toa predetermined fourth voltage if the device is in its other binarystate; and a feedback circuit operatively coupled to the input linewhich prevents the potential of the input line from considerablyexceeding a predetermined overshoot voltage.
 2. The read-biasing circuitof claim 1, further comprising a loading circuit operatively coupled tothe input line which provides a predetermined load voltage to the inputline.
 3. The read-biasing circuit of claim 1, further comprising anenable circuit having an enable line and operatively coupled to thefeedback circuit which prevents the read-biasing circuit from sensingthe binary state of a floating-gate memory device unless the potentialof the enable line substantially equals a predetermined enable voltage.4. The read-biasing circuit of claim 1, wherein the quick-chargingcircuit comprises a p-channel MOSFET transistor.
 5. The read-biasingcircuit of claim 1, wherein the quick-charging circuit comprises ann-channel MOSFET transistor.
 6. The read-biasing circuit of claim 1,wherein the feedback circuit comprises a p-channel MOSFET transistor, afirst n-channel MOSFET transistor, and a second n-channel MOSFETtransistor.
 7. The read-biasing circuit of claim 2, wherein the loadingcircuit comprises a p-channel MOSFET transistor.
 8. A high-speed sensorfor sensing the binary state of a floating-gate memory device,comprising: a differential amplifying circuit having a first input line,a second input line, and an output line which amplifies the differencebetween a potential at the first input line and a potential at thesecond input line; a memory array which stores a plurality of binarystates and having a column line; a quick-discharge circuit operativelycoupled to the column line of said memory array which quickly dischargesthe column line to a predetermined voltage; a read-biasing circuithaving an input line and an output line, the output line operativelycoupled to the first input line of said differential amplifying circuitand the input line operatively coupled to the column line of said memoryarray which quickly senses the potential at the column line afterdischarge; and a sense-reference circuit operatively coupled to thesecond input line of said differential amplifying circuit which providesa predetermined sense-reference potential.
 9. The high-speed sensor ofclaim 8, wherein the memory array comprises a plurality of floating-gatememory devices ordered in columns and rows and selectively coupled tothe column line.
 10. The high-speed sensor of claim 8, wherein thequick-discharge circuit comprises a transistor with a drain operativelycoupled to the column line of said memory array, a source operativelycoupled to ground, and a gate operatively coupled to an external clocksignal.
 11. The high-speed sensor of claim 8, wherein the read-biasingcircuit further comprises: a quick-charging circuit operatively coupledto the input line and the output line which quickly raises the potentialof the input line to a predetermined first voltage if the device is inone binary state and to a predetermined second voltage if the device isin its other binary state and the potential of the output line to apredetermined third voltage if the device is in one binary state and toa predetermined fourth voltage if the device is in its other binarystate; and a feedback circuit operatively coupled to the input linewhich prevents the potential of the input line from considerablyexceeding a predetermined overshoot voltage.
 12. The high-speed sensorof claim 8, wherein the sense-reference circuit comprises: aquick-charging circuit operatively coupled to the input line and theoutput line which quickly raises the potential of the input line to apredetermined first sense-reference voltage and the potential of theoutput line to a predetermined second sense-reference voltage; afeedback circuit operatively coupled to the input line which preventsthe potential of the input line from considerably exceeding apredetermined overshoot voltage; a quick-charging transistor operativelycoupled to the second input line of said differential amplifyingcircuit; and a reference memory device storing the sense-referencepotential and operatively coupled to the second input line of saiddifferential amplifying circuit.
 13. A method for sensing the binarystate of a floating-gate memory device, comprising the steps of:discharging the device to a predetermined voltage; sensing the potentialat the device after discharge; amplifying the sensed potential at thedevice; comparing the sensed potential at the device with an amplifiedpredetermined sense-reference potential; and amplifying the differencebetween the sensed potential at the device and the amplifiedpredetermined sense-reference potential.
 14. A computer, comprising: amicroprocessor; a timing unit; an I/O interface module; a volatilememory array; a non-volatile memory array comprised of a plurality ofselectively ordered floating gate memory devices and having an inputline and an output line; a quick-charging circuit operatively coupled tothe input line and the output line which quickly raises the potential ofthe input line to a predetermined first voltage if the device is in onebinary state and to a predetermined second voltage if the device is inits other binary state and the potential of the output line to apredetermined third voltage if the device is in one binary state and toa predetermined fourth voltage if the device is in its other binarystate; and a feedback circuit operatively coupled to the input linewhich prevents the potential of the input line from considerablyexceeding a predetermined overshoot voltage.
 15. A read-biasing andamplifying circuit, comprising: an input; an output; a first load havinga node; a first control device having a control input and a controlledsignal output, wherein the control input of the first control device iscoupled to the input, and the controlled signal output of the firstcontrol device is coupled to the node of the first load; a secondcontrol device having a control input, a controlled signal output, and asignal input, wherein the control input of the second control device iscoupled to the controlled signal output of the first control device, thesignal input of the second control device is coupled to the input, andthe controlled signal output of the second control device is coupled tothe output; a second load having a node, wherein the node of the secondload is coupled to the output; a third control device having a signalinput, wherein the signal input of the third control device is coupledto the output; wherein the second load comprises a fourth controldevice; wherein the node of the second load is a signal input of thefourth control device; and wherein the first load is a fifth controldevice, a control input of the fourth control device is coupled to acontrol input of the fifth control device, and a control input of thethird control device is coupled to the output.
 16. A read-biasing andamplifying circuit, comprising: an input; an output; a first load havinga node; a first control device having a control input and a controlledsignal output, wherein the control input of the first control device iscoupled to the input, and the controlled signal output of the firstcontrol device is coupled to the node of the first load; a secondcontrol device having a control input, a controlled signal output, and asignal input, wherein the control input of the second control device iscoupled to the controlled signal output of the first control device, thesignal input of the second control device is coupled to the input, andthe controlled signal output of the second control device is coupled tothe output; a second load having a node, wherein the node of the secondload is coupled to the output; a third control device having a signalinput, wherein the signal input of the third control device is coupledto the output; a fourth control device including a control input and acontrolled signal output; wherein the second load comprises a fifthcontrol device; wherein the node of the second load is a signal input ofthe fifth control device; and wherein the first load is a sixth controldevice, the control input of the fourth control device is coupled to acontrol input of the sixth control device, a control input of the thirdcontrol device is coupled to the output, and a the controlled signaloutput of the fourth control device is coupled to the controlled signaloutput of the first control device.
 17. A read-biasing and amplifyingcircuit, comprising: an input; an output; a first load having a node; afirst control device having a control input and a controlled signaloutput, wherein the control input of the first control device is coupledto the input, and the controlled signal output of the first controldevice is coupled to the node of the first load; a second control devicehaving a control input, a controlled signal output, and a signal input,wherein the control input of the second control device is coupled to thecontrolled signal output of the first control device, the signal inputof the second control device is coupled to the input, and the controlledsignal output of the second control device is coupled to the output; asecond load having a node, wherein the node of the second load iscoupled to the output; a third control device having a signal input,wherein the signal input of the third control device is coupled to theoutput; a fourth control device including a control input and acontrolled signal output; wherein the second load comprises a fifthcontrol device; wherein the node of the second load is a signal input ofthe fifth control device; and wherein the first load is a sixth controldevice, the control input of the fourth control device is coupled to acontrol input of the sixth control device, a control input of the thirdcontrol device is coupled to a controlled signal output of the thirdcontrol device, and the controlled signal output of the fourth controldevice is coupled to the controlled signal output of the first controldevice.
 18. A circuit, including: an input; an output; quick-chargingmeans for simultaneously raising potentials of a bit line and the outputand for continuing to raise the potential of the output when thepotential of the bit line is no longer raised; a load for a memorydevice being sensed, and a feedback means for preventing the potentialof the bit line from exceeding a read-bias potential.
 19. The circuit ofclaim 18, wherein the input is adapted to be operatively coupled to thebit line.
 20. The circuit of claim 18, wherein the output is adapted tobe operatively coupled to a microprocessor.
 21. The circuit of claim 18,wherein the quick-charging means is operatively coupled to the input andthe output.
 22. The circuit of claim 18, wherein the load is distinctfrom the quick-charging means.
 23. The circuit of claim 22, wherein theload is a resistive load.
 24. The circuit of claim 23, wherein theresistive load is a p-channel MOSFET.
 25. The circuit of claim 18,wherein the feedback means is operatively coupled to the input.
 26. Thecircuit of claim 25, wherein the feedback means includes a p-channelMOSFET operatively coupled to a first n-channel MOSFET, and a secondn-channel MOSFET operatively coupled to the first n-channel MOSFET. 27.The circuit of claim 25, wherein the feedback means includes ann-channel MOSFET operatively coupled to a first p-channel MOSFET, and asecond p-channel MOSFET operatively coupled to the first p-channelMOSFET.
 28. A circuit, including: an input; an output; quick-chargingmeans for simultaneously raising potentials of a bit line and theoutput; a load for a memory device being sensed, and a feedback meansfor preventing the potential of the bit line from exceeding a read-biaspotential.
 29. The circuit of claim 28, wherein the quick-charging meansincludes means for continuing to raise the potential of the output whenthe potential of the bit line is no longer being raised.
 30. The circuitof claim 28, wherein the load is distinct from the quick-chargingdevice.
 31. The circuit of claim 30, wherein the load is a resistiveload.
 32. The circuit of claim 31, wherein the resistive load is ap-channel MOSFET.
 33. The circuit of claim 28, wherein the feedbackmeans is operatively coupled to the input.
 34. The circuit of claim 33,wherein the feedback means includes a p-channel MOSFET operativelycoupled to a first n-channel MOSFET, and a second n-channel MOSFEToperatively coupled to the first n-channel MOSFET.
 35. The circuit ofclaim 33, wherein the feedback means includes an n-channel MOSFEToperatively coupled to a first p-channel MOSFET, and a second p-channelMOSFET operatively coupled to the first p-channel MOSFET.
 36. A circuit,comprising: an input; an output; a first transistor including a sourceand a well both connected to a first voltage, the first transistorincluding a gate and a drain; a second transistor including a source anda well both connected to the first voltage, the second transistorincluding a gate and a drain, wherein the second transistor gate isconnected to the first transistor gate and a second voltage; a thirdtransistor including a source and a well both connected to the firstvoltage, the third transistor including a gate and a drain bothconnected to the output; a fourth transistor including a sourceconnected to the second voltage, a gate connected to the input, and adrain connected the first transistor drain; and a fifth transistorincluding a source connected to the input, a gate connected to thefourth transistor drain, and a drain connected to the output.
 37. Thecircuit of claim 36, wherein at least one of the first transistor,second transistor, and third transistor is a p-channel transistor. 38.The circuit of claim 36 wherein at least one of the third transistor andfourth transistor is an n-channel transistor.
 39. The circuit of claim36, wherein the first, second, and third transistors are p-channeltransistors, and the fourth and fifth transistors are n-channeltransistors.
 40. The circuit of claim 36, wherein the first voltage isVcc.
 41. The circuit of claim 36, wherein the second voltage is Vss. 42.The circuit of claim 36, wherein the third transistor is aquick-charging device adapted to operate in a saturated region for quickcharging of a bit line and adapted to be in an off state during sensingof a bit line.
 43. The circuit of claim 36, wherein the secondtransistor, during a sensing operation, operates in a linear region andprovides current and acts as a load.
 44. The circuit of claim 36,wherein the first transistor, fourth transistor, and third transistoroperate as a feedback circuit during a sensing operation.
 45. A circuit,comprising: an input; an output; a first transistor including a sourceand a well both connected to a first voltage, the first transistorincluding a gate and a drain; a second transistor including a source anda well both connected to the first voltage, the second transistorincluding a gate and a drain, wherein the second transistor gate isconnected to the first transistor gate and a second voltage; and afeedback biasing circuit, wherein the feedback biasing circuit consistsof: a third transistor including a source and a well both connected tothe first voltage, the third transistor including a gate and a drainboth connected to the output; a fourth transistor including a sourceconnected to the second voltage, a gate connected to the input, and adrain connected the first transistor drain; and a fifth transistorincluding a source connected to the input, a gate connected to thefourth transistor drain, and a drain connected to the output.
 46. Thecircuit of claim 45, wherein at least one of the first transistor,second transistor, and third transistor is a p-channel transistor. 47.The circuit of claim 45, wherein at least one of the third transistorand fourth transistor is an n-channel transistor.
 48. The circuit ofclaim 45, wherein the first, second, and third transistors are p-channeltransistors, and the fourth and fifth transistors are n-channeltransistors.
 49. The circuit of claim 45, wherein the first voltage isVcc.
 50. The circuit of claim 45, wherein the second voltage is Vss. 51.The circuit of claim 45, wherein the third transistor is aquick-charging device adapted to operate in a saturated region for quickcharging of a bit line and adapted to be in an off state during sensingof a bit line.
 52. The circuit of claim 45, wherein the secondtransistor, during a sensing operation, operates in a linear region andprovides current and acts as a load.
 53. A read-biasing and amplifyingsystem, comprising: a first read-biasing and amplifying circuit; asecond read-biasing and amplifying circuit; and a differential amplifierconnected between the first circuit and the second circuit.
 54. Thesystem of claim 53, wherein at least one of the first circuit and thesecond circuit include: an input; an output; a first load having a node;a first control device having a control input and a controlled signaloutput, wherein the control input of the first control device is coupledto the input, and the controlled signal output of the first controldevice is coupled to the node of the first load; a second control devicehaving a control input, a controlled signal output, and a signal input,wherein the control input of the second control device is coupled to thecontrolled signal output of the first control device, the signal inputof the second control device is coupled to the input, and the controlledsignal output of the second control device is coupled to the output; asecond load having a node, wherein the node of the second load iscoupled to the output; a third control device having a signal input,wherein the signal input of the third control device is coupled to theoutput; wherein the second load comprises a fourth control device;wherein the node of the second load is a signal input of the fourthcontrol device; and wherein the first load is a fifth control device, acontrol input of the fourth control device is coupled to a control inputof the fifth control device, and a control input of the third controldevice is coupled to the output.
 55. The system of claim 53, wherein atleast one of the first circuit and the second circuit include: an input;an output; a first load having a node; a first control device having acontrol input and a controlled signal output, wherein the control inputof the first control device is coupled to the input, and the controlledsignal output of the first control device is coupled to the node of thefirst load; a second control device having a control input, a controlledsignal output, and a signal input, wherein the control input of thesecond control device is coupled to the controlled signal output of thefirst control device, the signal input of the second control device iscoupled to the input, and the controlled signal output of the secondcontrol device is coupled to the output; a second load having a node,wherein the node of the second load is coupled to the output; a thirdcontrol device having a signal input, wherein the signal input of thethird control device is coupled to the output; a fourth control deviceincluding a control input and a controlled signal output; wherein thesecond load comprises a fifth control device; wherein the node of thesecond load is a signal input of the fifth control device; and whereinthe first load is a sixth control device, the control input of thefourth control device is coupled to a control input of the sixth controldevice, a control input of the third control device is coupled to theoutput, and a the controlled signal output of the fourth control deviceis coupled to the controlled signal output of the first control device.56. The system of claim 53, wherein at least one of the first circuitand the second circuit include: an input; an output; a first load havinga node; a first control device having a control input and a controlledsignal output, wherein the control input of the first control device iscoupled to the input, and the controlled signal output of the firstcontrol device is coupled to the node of the first load; a secondcontrol device having a control input, a controlled signal output, and asignal input, wherein the control input of the second control device iscoupled to the controlled signal output of the first control device, thesignal input of the second control device is coupled to the input, andthe controlled signal output of the second control device is coupled tothe output; a second load having a node, wherein the node of the secondload is coupled to the output; a third control device having a signalinput, wherein the signal input of the third control device is coupledto the output; a fourth control device including a control input and acontrolled signal output; wherein the second load comprises a fifthcontrol device; wherein the node of the second load is a signal input ofthe fifth control device; and wherein the first load is a sixth controldevice, the control input of the fourth control device is coupled to acontrol input of the sixth control device, a control input of the thirdcontrol device is coupled to a controlled signal output of the thirdcontrol device, and the controlled signal output of the fourth controldevice is coupled to the controlled signal output of the first controldevice.
 57. The system of claim 53, wherein at least one of the firstcircuit and the second circuit include: an input; an output; a firsttransistor including a source and a well both connected to a firstvoltage, the first transistor including a gate and a drain; a secondtransistor including a source and a well both connected to the firstvoltage, the second transistor including a gate and a drain, wherein thesecond transistor gate is connected to the first transistor gate and asecond voltage; a third transistor including a source and a well bothconnected to the first voltage, the third transistor including a gateand a drain both connected to the output; a fourth transistor includinga source connected to the second voltage, a gate connected to the input,and a drain connected the first transistor drain; and a fifth transistorincluding a source connected to the input, a gate connected to thefourth transistor drain, and a drain connected to the output.
 58. Thesystem of claim 53, wherein at least one of the first circuit and thesecond circuit include: an input; an output; a first transistorincluding a source and a well both connected to a first voltage, thefirst transistor including a gate and a drain; a second transistorincluding a source and a well both connected to the first voltage, thesecond transistor including a gate and a drain, wherein the secondtransistor gate is connected to the first transistor gate and a secondvoltage; and a feedback biasing circuit, wherein the feedback biasingcircuit consists of: a third transistor including a source and a wellboth connected to the first voltage, the third transistor including agate and a drain both connected to the output; a fourth transistorincluding a source connected to the second voltage, a gate connected tothe input, and a drain connected the first transistor drain; and a fifthtransistor including a source connected to the input, a gate connectedto the fourth transistor drain, and a drain connected to the output. 59.The system of claim 53, wherein at least one of the first circuit andthe second circuit include: an input; an output; quick-charging meansfor simultaneously raising potentials of a bit line and the output; aload for a memory device being sensed, and a feedback means forpreventing the potential of the bit line from exceeding a read-biaspotential.
 60. The system of claim 53, wherein at least one of the firstcircuit and the second circuit include: an input; an output;quick-charging means for simultaneously raising potentials of a bit lineand the output and for continuing to raise the potential of the outputwhen the potential of the bit line is no longer raised; a load for amemory device being sensed, and a feedback means for preventing thepotential of the bit line from exceeding a read-bias potential.
 61. Acircuit, including: a bit line input; an output; quick-charging meansfor raising potentials of a bit line and the output and for continuingto raise the potential of the output when the potential of the bit lineis no longer raised; a load for a memory device being sensed, and afeedback means for preventing the potential of the bit line fromexceeding a read-bias potential.
 62. A circuit, including: an input; anoutput; quick-charging means, operatively coupled to the input and theoutput, for simultaneously raising potentials of a bit line and theoutput and for continuing to raise the potential of the output when thepotential of the bit line is no longer raised; a resistive load for amemory device being sensed, wherein the load is distinct from thequick-charging means; and a feedback means for preventing the potentialof the bit line from exceeding a read-bias potential.
 63. The circuit ofclaim 61, wherein the resistive load is a p-channel MOSFET.
 64. Acircuit, including: an input adapted to be operatively coupled to thebit line; an output adapted to be operatively coupled to amicroprocessor; quick-charging means, operatively coupled to the inputand the output, for simultaneously raising potentials of a bit line andthe output and for continuing to raise the potential of the output whenthe potential of the bit line is no longer raised; a resistive load fora memory device being sensed, wherein the load is distinct from thequick-charging means; and a feedback means, operatively coupled to theinput, for preventing the potential of the bit line from exceeding aread-bias potential, wherein the feedback means includes a p-channelMOSFET operatively coupled to a first n-channel MOSFET, and a secondn-channel MOSFET operatively coupled to the first n-channel MOSFET. 65.The circuit of claim 64, wherein the resistive load is a p-channelMOSFET.